High “Application per Silicon size” Ratio

The chip utilization in terms of Application Per Silicon Size is very high, increasing with application complexity. Our parallel processing hardware implementation of DSP applications, can reach far superior results compared with line-by-line processing in DSP as the chip utilization in terms of computing power or MIPS is very high and can exceed the 500,000 MIPS (8 bit) in Digital Signal Processing (DSP) applications.

The main reasons for this utilization advantage are:

·        The largest FPCL logic core size is about 2.5MBytes (while the size of the largest FPGA logic core in known FPGAs is only about 200KBytes for the same geometry and the same dye size).

·         Enhanced architecture features:

o        Any cell write ability

o        Ability to combine cells to create larger cells

o        Full connectivity

Surprisingly short time from Idea to Product

80% of the development time from idea to product may be saved by making obsolete many currently needed development stages, using the high level language development environment, the PC based environment and the extremely fast one to one (which may reach real time) simulation / emulation development tools.

This is possible due to the following architecture qualities:

·         Fixed delay and predictable timing throughout the chip

·         One-to-one architecture emulation on PC.

·         Ability to use abstract high-level language (including C++)

·         Straightforward one-to-one migration from FPCL to ASIC

·         I/O pin assignment programmability allows significant manufacturing flexibility.

To compare the development stages between Common Programming and Cellot Solution click the following link: Programming Process.

Low Manufacturing Cost

FPCL technology can “map itself” and define faulty cells. Hence, what seems to be a faulty chip in other methods can be used seamlessly. Therefore, significant price reduction is achieved due to the usability of “faulty” dies and hence the wafers’ higher production yields. The manufacturing cost of FPCL chips is expected to be low and grow linearly (rather than exponentially) with die size. Since Cells and Switches are replaceable, most of the chip has redundancy. Any cell or few cells left unused intentionally, may restore the device which otherwise would be considered faulty. This increases the yield significantly and reduces the device-manufacturing price.

Failures Immunity

FPCL technology can “map itself” and define faulty cells even while in active application. This enables on the fly failure discovery and fixing.

No Timing Issues

Many of the biggest issues in developing applications with FPGA are associated with timing. The delay of a circuit implemented in an FPGA is mostly due to routing delays rather than logic block delays, and most of an FPGA’s area is devoted to programmable routing. In FPCL, the delays are fixed and determined by the input clocks, therefore there are no timing issues. This allows the realization of real time simulation and allows dramatic advantages over present technology.

One-to-One Simulation 

The device can be emulated on a PC. As the simulator uses this chip emulation it ensures that any working simulated application works faultlessly when downloaded onto the programmable device, thus dramatically shortening the last stages of tedious phases of "on-board" debugging. The simulation is a “one-to-one” simulation, which means that besides the ability to simulate the function, it simulates the exact way the code runs on the device. Therefore, if the application works on the simulator, the application will work on the device!

C++ Support

Few classes, appropriate library and a simple interface to the FPCL Developer Environment are used to support any software engineer (no need for hardware expertise) and any hardware engineer who is familiar with C++ to utilize the C++ development environment in order to:

·         Simulate any hardware application

·         Create any hardware application using the FPCL emulation

·         Create any signal generation

·         Manipulate result (e.g. see graphic results in logarithmic view)

·         Add commands to the FPCL Compiler

·         Manipulate the schematic diagram

·         Add features such as wizard buttons to the FPCL Developer Environment

Features that are developed utilizing the C++ Support can be easily integrated into the basic FPCL Developer Environment (which is also written in C++). For example:

The compiler has been opened to support languages such as Verilog. This support can be implemented both by enhancing the FPCL Developer Environment code or using the C++ Support and then integrating (or not) the code into the FPCL Developer environment. It is seamless to the Verilog user if the code is integrated into the FPCL Developer environment or not (nevertheless, now it is integrated).

Manufacturing Flexibility

As there is no practical limitation on connectivity using the internal cross connection, the I/O pins can be set before the application is designed. Once the interface is determined, the electronics (such as the card which the device is placed on) can be built while the application is realized with the PC development tools.

Migration to ASIC

The migration from FPCL to ASIC entry is automatic, quick, and does not require a new technology that frequently creates new “vicious circles” of re-design and debugging. Nevertheless, our solution meets the trend in the market of extended usage in Programmable Devices as a replacement to ASIC. Our low cost and high performance chips, will give us the advantage in competing on certain ASIC market share. (see also "Structured Cellot ASIC"

An ASIC – FPCL combination that will enable Application Specific with programmable capabilities can be customized to clients’ needs.

Ever Green Design

Our technology offers an “Ever Green” solution. Unlike most of the existing Electronic Designs, our hardware architecture, the core-IPs and the user developed applications are Chip geometry independent. Along the future industry technological evolution, and with the introduction of new geometries, a new design will not be required. An FPCL complex design of today may be “as is” ported and implemented on future FPCL devices, years from now. This feature will provide customers with incredible savings and incentive to use the FPCL devices. This feature relay to the fractal like architecture: when smaller cells are created in one geometry, these smaller cells can be combined to create larger cells. On the other hand – larger cells can always seamlessly function as smaller cells.

Time Sharing

FPCL is also exceptionally suited for time-sharing applications. Once an application is implemented, a new cell is assigned to each application cell to store the application cell output for each clock. In such manner we have shown an example of more than 20,000 FIR Filters implemented on a single (medium) FPCL device.