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FPCL Potential Markets The FPCL technology can be used in the PLD, DSP, structured array ASIC, super computers, evolvable hardware and other markets.
The PLD Market The FPCL is a Programmable Logic Device. Although it is equipped with multi‑feature capabilities (see the FPCL Features) it is also highly efficient when used for common PLD applications. The following points will enable you to compare the efficiency of the FPCL with other PLDs:
See also High "Application Per Silicon size" Ratio The DSP Market The FPCL can handle very complex applications. As such, it is suitable for Digital Signal Processing applications which are normally implemented by a Digital Signal Processor. It may seem that DSP implementation has advantage over common hardware implementation in the development simulation stage, as both the simulation and the implementation can be written in a high level language such as “C” and the conversion of the simulation to a working application seems easier. Nevertheless, this advantage becomes irrelevant because the FPCL Developer Environment utilizes a "mirror" device which provides "one-to-one simulation. Comparing the operation of DSP and FPCL applications: Digital Signal Processors can only implement one command at a time while the FPCL may implement thousands of commands in parallel. This provides a great advantage over DSP implementation. Combined DSP and FPCL The FPCL has a controller to handle seamlessly the "Built In Test and Auto Recovery" feature (see Failures Immunity). Note that the controller (and this feature) can be eliminated from FPCL Devices. However, as it is implemented in the device, users can benefit from its use for the application. Increasing the power of the controller is the same as integrating the FPCL with a DSP and therefore providing the benefits of both DSP and Programmable Hardware. The FPCL can be easily converted into ASIC (see Migration to ASIC). Nevertheless, a ROM-based device can be prepared so that it is similar to a Field Programmable device (an FPCL). Once the application is satisfactory and tested in its environment, the user can immediately use this ROM based device. Then, as only one or two masks are required to set the ROMs to the specified values and eliminate the reprogrammable interconnect, a (Structured) ASIC can be implemented in a short time and at a low cost. Super Computers Apart from the very high FPCL applicability (see High "Application Per Silicon size" Ratio) in which super real-time computing power can be achieved, a small number of FPCL devices can be utilized to convert a regular computer into a super computer. The basis for supercomputer implementation is a collection of several FPCL devices each of which is programmed to carry out a required operation. A host computer stores the code that must be loaded into each device so as to enable it to operate. While one device is executing the application, a second is connected to the host as normal memory allowing previous results to be read there from or for new code to be loaded, and at the same time the code for effecting the required connections and loading the required data may be loaded into the third device. Upon completion of an application by the currently running device, the states of each device change, and the host is connected to the device that has just finished its task for reading the result and loading a new implementation. Each implementation may therefore be effected in hardware. This is much faster than can be done with a normal CPU using software. Downloading new data to the devices is time-consuming and is done in parallel with the operation of a different device and therefore represents a transparent operation not demanding any real-time overhead. This technique can be useful when very fast real-time computing is required (as in configurable computers). The host computer will change the task to be implemented as needed on one device, while in the other device it fetches the result of the previous instruction. Outer Space applications One of the main problems in outer space is the premature aging phenomena. Using the Built In Test and Auto-Recovery feature (see Failures Immunity) increases the life-cycle of the FPCL enabling the user a more flexible and enhanced PLD in a hostile environment. Evolvable Hardware In order to specify the application portion, each cell is programmed with a specific code. The FPCL cells can be programmed to create the required application and can also be programmed as a result of the running application by the application itself. In other words, each cell (in any re-programmable size) can be used as an application portion (Look Up Table or LUT), as regular memory or as both. This is the basis for Evolvable Hardware features. To learn about the ability of the running application to change the routing, please refer to other Cellot documentation. Neural Networks There is a professional opinion that the FPCL can be useful for Neural Network applications. Cellot has not evaluated this yet.
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